The present invention relates generally to integrated circuit (IC) designs, and more particularly to a word line driver for a memory device.
A typical static random access memory (SRAM) device often includes a word line driver for receiving a word select signal from a decoder. The word line driver usually includes inverters made of devices that are short in channel length and wide in width. These inverters are used for adjusting voltage levels on word lines during programming and reading operations. The inverter usually includes a couple of PMOS and NMOS transistors serially connected between a supply voltage and a complementary supply voltage for generating an inverted output signal in response to an input signal.
One challenge for improving the power efficiency of the word line driver is to reduce its leakage current during a standby mode. Conventionally, the word line driver includes two stages of inverters, each having a set of serially coupled PMOS transistor and NMOS transistor. During the standby mode, a substantial leakage current would occur at the gate of the NMOS transistor within the second stage inverter, thereby wasting electrical power. For example, in a conventional word line driver having an NMOS transistor with a 3.8 μm width and a 0.1 μm length implemented in its second stage inverter, the gate leakage current of the transistor can reach about 589 nA during the standby mode where the supply voltage is lowered to about 1.2 volts. In such scenario, the total leakage current of the word line driver is about 864 nA. This shows that the gate leakage current is a predominant portion of the total standby leakage current.
Thus, what is needed is a word line driver with reduced gate leakage current in the standby mode.